Computer aided design (CAD) systems are used to design complex integrated circuits or dies. Schematic designs are created using such CAD systems which describe the integrated circuit components and interconnections between components which will be fabricated within integrated circuit dies.
An IC design can contain many subdesigns (modules) which likewise can contain subdesigns therein. Under this topology, the top level of an IC design typically includes a hierarchical structure of interconnected circuit modules. The overall system is the top most module. The top level module does not usually include any reference to gates or other circuits, but rather refers more to the function accomplished by the top or macro level component(s) which are the largest functional component(s) in the design.
Once a schematic circuit design has been created using CAD systems, it is output as a netlist. Netlists are computer files which contain a textual or character based description of the integrated circuits and the relationships between the circuits or cells that comprise an electronic circuit described by the netlist or schematic design.
Netlists can be organized in the hierarchical or the flat form. A flat data netlist contains multiple copies of the circuit modules without boundary descriptions found in hierarchical representations, usually consisting of module or cell instance names. For example, a flat data netlist will list one or more flat paths describing a string of components that are connected at a highest level in the circuit design hierarchy through a lowest component without hierarchical boundaries such as CellA or CellB. In other words, a flat path is a path statement from a starting place, usually the highest point in that particular path, to a specified endpoint marker or either the lowest or bottom-most primitive component in a particular current or circuit path. The start or stop points can also be selected based upon a desire to test a segment within a larger circuit path.
Chip designs are tested using a variety of computer programs. One type of electronic design automation (EDA) system used to evaluate and perform error checking on the netlist after the design is compiled includes verification systems such as an electrical rule check (ERC) programs, layout versus schematic (LVS) programs as well as simulation programs such as Spice. ERC programs look at a netlist schematic and verifies markers or other specific components are present or not present within the schematic design. ERC programs evaluate circuit designs which test for faults or design flaws that are caused by improper combinations of circuit elements or entities with respect to properties or markers placed in the netlist as well as with respect to critical net names or other circuit attributes. The cell boundaries are checked to ensure the netlist net names have not been changed at a higher level which then creates a different set of net descriptions as cell boundaries are traversed (cell boundaries are where nets enter a cell at a port in the cell). In some cases it is desirable to have consistent net identifications for interconnected nets. Thus, a property can exist on a cell which is changed that corresponds initially to a higher level then a designer changes the higher level net reference, which then creates a discontinuity in net name path identity.
Diagnostic or error checking programs use either flat data or hierarchical data netlists as inputs, depending on the system and checks involved. Many types of conventional verification systems require flat data extracts from hierarchical netlists to perform verification functions. This can take a great deal of time when dealing with very large systems such as a DRAM. For example, a DRAM can have hundreds of millions of cells which the flat list search system must go through and create an absolute path statement to populate the flat data file. Thus, when changes are made to the design, it is necessary to recompile the chip design from a hierarchical format to a flat format. The need to frequently convert from one format to another adds lengthy delays to the chip design project. Also, flat netlists are much larger and hence require more storage, e.g., disk space. Consequently, it is not desirable to be required to create multiple flat data extracts to perform rule checking if it can be avoided. Thus, a need exists to improve the ability for verification systems to determine if designs have errors using hierarchical netlists rather than recompiling flat data extracts for each design change.